The present invention relates to the field of computer memory address mapping. More particularly, the present invention relates to a device for more efficiently converting a linear configuration virtual memory address to a physical memory address via an XY coordinate configuration system.
Electronic systems and circuits have made a significant contribution towards the advancement of modem society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices; video equipment, and telephone systems include computer graphics systems that have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Usually, applications designed to provide these results utilize information stored in a memory of a computer system. To be effective and operate properly, most graphics applications require the information to be communicated efficiently to and from the memory via a computer graphics system.
Computer graphics""systems typically provide a method for interfacing between a computer and a user. Often, this interfacing involves the graphical representation of images (graphics) on a display screen, other visualization device or a hard copy printout. Graphics are generated by computer graphics systems that simulate and display images of real or abstract objects. Graphics enable a user to visualize and comprehend the configuration of a single object or the interaction and relationships between a group of objects. The images usually comprise pictures in which the objects remain still, or video displays in which the objects move. Most modern computer graphics systems are interactive, permitting a user to input changes to a display or modify the images on the fly.
In a complex or three dimensional (3D) computer generated graphical image, objects are typically described by graphics data models. These coverage masks typically define the shape of the object, the object""s attributes, and where the object is positioned. The shape of the object is normally described in terms of xe2x80x9cprimitivesxe2x80x9d, which usually comprise mathematically described circular disks, vectors, polygons or polyhedra. The graphics information is input into memory and a central processing unit (CPU) interprets instructions and image data in order to perform the appropriate processing. Some computer graphics systems may include special-purpose processors, each custom tailored to specific graphics functions. The main graphical processing function of the CPU (or special-purpose processors) is to simplify very complex models by taking the specifications of graphical primitives specified by application programs and to assign pixels parameter values that best represent characteristics of an image.
In most computer graphic systems an image is represented as a raster (an array) of logical picture elements (pixels). A pixel corresponds to a small area of the image, usually a rectangle (but it can be other shapes). The computer graphics system assigns parameter values to each pixel as part of a rasterization process. Rasterization can proceed on a pixel basis or primitive basis. These parameter values are digital values corresponding to certain attributes of the image (e.g. color, depth, etc.) measured over a small area of the image represented by the pixel. Typically each graphical image is represented by thousands of combined pixels. The pixel parameter values associated with an image are usually stored in a portion of a memory referred to as a frame buffer. The resolution and detail of the image are largely determined by the number of pixels in the frame buffer. The number of bits that are used for each pixel defines the depth of the frame buffer and determines properties such as how many colors can be represented on a given system. For example, a 1-bit-deep frame buffer allows only two colors. Frame buffers play an important role in rasterization.
A frame buffer is a portion of a memory that stores pixel information associated with an image. There are usually a number of frame buffers in a computer graphics system. The frame buffers may be scattered throughout a memory and are not necessarily contiguous. Frame buffers often comprise information associated with a particular image configuration system because some data configuration or reference systems are easier and more efficient for a computer graphics system to manipulate. For example, frame buffers are often configured and allocated memory space in a manner that accommodates a two dimensional xe2x80x9cXYxe2x80x9d tile coordinate system.
Numerous computer graphics systems prefer to operate in a two dimensional xe2x80x9cXYxe2x80x9d tile coordinate system. FIG. 1 is a conceptual example of an XY coordinate image configuration system 100. Image configuration system 100 includes 2 by 2 pixel regions, such as pixel region 191, set in 16 by 16 region tiles 170 through 185 arranged on an xe2x80x9cx axisxe2x80x9d 110, xe2x80x9cy axisxe2x80x9d 120. Image configuration system 100 includes xe2x80x9cz axisxe2x80x9d 130. The 2 by 2 pixel regions can be arranged in any place within the texture images and can slide around, sometimes it may fall in a single tile, sometimes it may fall within two tiles and other times it may fall within four tiles. xe2x80x9cSlicesxe2x80x9d of a 3D image are defined by the xe2x80x9cz axisxe2x80x9d, for example pixel region 191 is in slice 133 and pixel region 192 is in slice 134. Slice 134 is actually another xy plane at a different location on the Z axis and pixel region actually lies in tiles (not shown) behind tiles 275, 276, 279 and 280. While a pixel region may move around the coordinate system, the boundaries of the tiles do not change and the tiles are defined by the particular XY coordinates. There are numerous tile boundary configurations, for example a 64 kilo-byte (KB) tile comprising 128 by 128 pixels and each pixel being define by a 32 bit parameter value.
Operating in a tile, XY coordinate system provides certain advantages for most graphics systems and a tile configuration system is particularly beneficial towards the end of a typical graphics pipeline. For example, scan conversion operations can be performed on a number of tiles in parallel permitting much faster scan conversions. Thus, a number of graphics buffers (e.g., image buffer, frame buffer, Z buffer, texture map buffer, etc.) are organized to reference stored data by two-dimensional tiled configuration addresses. While utilizing reference addresses that are configured in accordance with a tile configuration system is efficient for most computer graphics systems, it is not necessarily optimal in all situations.
Memory hardware is usually limited to specific configurations in which the physical location of storage spaces are arranged in a consecutive fashion and are addressed accordingly. Since memory hardware is typically set to a predefined physical location, address references in applications or systems that utilize different configuration schemes are virtual addresses (referencing a xe2x80x9cvirtual memoryxe2x80x9d) that are translated into addresses that refer to an actual physical storage location. Efficient computer systems usually handle the translations between virtual and physical reference addresses and make the distinction between a physical address that identifies a particular location in memory and a virtual address that identifies or refers to a piece of information transparent to a user.
Differing applications and systems within a computer system often prefer to communicate with memories utilizing reference addresses arranged in particular configurations. Tiled memory addressing is usually not conducive to user processes or applications that formulate memory read and write requests in a linear address format and expect responses in a linear configuration. For example, user graphics processes or applications are typically designed to refer to a contiguous linear virtual address xe2x80x9cspacexe2x80x9d in which each scan line of the graphics buffer is linearly addressable. The addresses are in a virtual configuration since physical addressable space limitations of memory hardware may be smaller than the linear virtual addresses and the information may have to be downloaded to a memory in sections. Again it is preferable for the translations and conversions to be handled automatically and transparent to the user. As discussed above, the objective of most computer graphics systems is to create a graphical image based upon information related to graphics images stored in a memory. Therefore, it is very important for information to be communicated to and from a memory in an efficient manner, including translations or conversions between different virtual address configurations and physical memory addresses.
What is required is a system and method that efficiently maps a linear configuration virtual memory address to a physical memory address via a tile XY coordinate configuration system. The system and method should permit applications that specify virtual memory read and write addresses in a linear configuration to directly access a physical memory address via a system operating in a tile XY coordinate configuration system. The system and method should also facilitate access of tile configuration frame buffers in a physical memory by computer graphics applications that are designed to designate frame buffer addresses in a virtual linear configuration.
The present invention is a system and method that efficiently converts a linear virtual address to a physical memory address via a tile XY coordinate configuration system. The system and method permits applications that specify read and write addresses in a linear virtual address configuration to directly access a physical memory address via a system operating in a tile XY coordinate configuration system. The system and method of the present invention facilitates access of tile configuration frame buffers in a physical memory by computer graphics applications that are designed to designate frame buffer virtual addresses in a linear configuration.
In one embodiment of the present invention a tile frame buffer linear mapping system facilitates memory accesses utilizing a linear virtual address to designate a physical memory address via a tile XY coordinate configuration system. A linear XY address converter converts a linear address into a tile XY coordinate address. Then a memory storing a descriptor table is utilized to identify an translation buffer base frame offset associated with the particular frame buffer comprising the information to be accessed. Based upon the translation buffer base frame offset forwarded by the descriptor table and a tile identifier, a circuit generates a tile offset into the actual frame buffer. A translation buffer stores a number of physical addresses of locations in a physical memory that store information associated with a base pixel of a graphics tile and determines an index associated with particular graphics tile. Then another circuit the physical memory address of the base pixel of the tile with the tile XY address to determine the physical memory location of information associated with a particular pixel.